A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.