US Patent 11269778 Mapping supporting non-sequential writes at sequentially-written memory devices

A system comprising integrated circuit (IC) dice having memory cells and a processing device coupled to the IC dice. The processing device to perform operations including: intercepting an input/output (IO) write request directed at the IC dice; causing a device mapping logic to enter an initial state associated with a first group of memory cells of the IC dice; caching a write pointer that includes a location within the first group of memory cells; transitioning the device mapping logic from the initial state to a sequential IO state; and, in response to determining the IO write request is directed to the location of the write pointer, causing data associated with the IO write request to be sequentially written to IC dice starting at the location of the write pointer.