Patent attributes
The present disclosure provides an impedance measurement circuit for measuring and detecting variations in an impedance under test, and methods of operating the impedance measurement circuit. The impedance measurement circuit comprises a plurality of converts, including at least two digital-to-analog converters (DACs). The DACs together alternate between a first mode of operation and a second mode of operation. In the first mode, a first one of the DACs is operational to convert a first digital input signal to a first analog output using a first hardware component, and a second one of the DACs is operational to convert a second digital input signal to a second analog output using a second hardware component. In the second mode, the first one of the DACs is operational to convert the first digital input signal to the first analog output using the second hardware component, and the second one of the DACs is operational to convert the second digital input signal to the second analog output using the first hardware component. By alternating between the first and second modes, the first and the second hardware components are alternately used in the first DAC and the second DAC to perform the respective DAC's conversion operations. Each hardware component may be associated with an intrinsic noise power that causes magnitude errors in the respective DAC's output. Furthermore, the DACs may be arranged such that magnitude errors in the first DAC and magnitude errors in the second DAC cause opposing errors in the impedance measurement made by the impedance measurement circuit. Therefore, by alternating between the first and the second modes, errors in the impedance measurements performed by the impedance measurement circuit are stabilised, or ratiometrically cancelled, over time.
