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US Patent 11281406 Memory system
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Patent
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Date Filed
August 28, 2020
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Date of Patent
March 22, 2022
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Patent Application Number
17005724
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Patent Citations
US Patent 10720221 Semiconductor storage device and memory system in which control circuit of the semiconductor storage device executes calibration operation according to timing at which data is read from another semiconductor storage device
US Patent 10725909 Memory device controlling including reading from a first memory and writing to a second memory based on timing and control signals
US Patent 10685702 Memory array reset read operation
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US Patent 10706940 Memory system
Patent Inventor Names
Naoaki Kanagawa
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11281406
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Patent Primary Examiner
Charles Rones
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CPC Code
G06F 3/0679
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G11C 16/32
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G11C 16/0483
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G06F 3/0659
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H01L 2225/06506
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H01L 2225/0651
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H01L 25/0657
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G06F 3/0604
0
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