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US Patent 11282961 Enhanced bottom dielectric isolation in gate-all-around devices
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Patent
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Date Filed
March 24, 2020
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Date of Patent
March 22, 2022
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Patent Application Number
16828162
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Patent Citations
US Patent 10453824 Structure and method to form nanosheet devices with bottom isolation
US Patent 10256158 Insulated epitaxial structures in nanosheet complementary field effect transistors
US Patent 10720431 Methods of fabricating semiconductor devices having gate-all-around structure with oxygen blocking layers
US Patent 10032867 Forming bottom isolation layer for nanosheet technology
US Patent 10170638 Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer
Patent Inventor Names
Ruilong Xie
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Andrew Greene
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Julien Frougier
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Kangguo Cheng
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11282961
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Patent Primary Examiner
Changhyun Yi
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CPC Code
H01L 2029/7858
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H01L 29/785
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