US Patent 11302395 Apparatus having transistors with raised extension regions

Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric overlying a semiconductor having a first conductivity type, a conductor overlying the dielectric, first and second extension region bases formed in the semiconductor and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.