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US Patent 11308026 Multiple busses interleaved in a systolic array

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
June 29, 2020
Date of Patent
April 19, 2022
Patent Application Number
16915777
Patent Citations
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US Patent 10879904 Application specific integrated circuit accelerators
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US Patent 10817260 Reducing dynamic power consumption in arrays
Patent Citations Received
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US Patent 12067375 Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
0
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US Patent 11853156 Error checking for systolic array computation
0
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US Patent 11880682 Systolic array with efficient input reduction and extended array performance
0
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US Patent 11507452 Error checking for systolic array computation
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US Patent 11762803 Multiple accumulate busses in a systolic array
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US Patent 11842169 Systolic multiply delayed accumulate processor architecture
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11308026
Patent Primary Examiner
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Eric Coleman

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