Patent attributes
The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.
