Patent attributes
A flash array provided in embodiments includes a controller and a solid state disk group. The controller counts a data volume of invalid data included in each of a plurality of stripes, and select at least one target stripe from the plurality of stripes. The target stripe is a stripe that includes a maximum volume of invalid data among the plurality of stripes. Then, the controller instructs the solid state disk group to move valid data in the target stripe, and instructs the solid state disk group to delete a correspondence between a logical address of the target stripe and an actual address of the target stripe. This can reduce write amplification, thereby prolonging a life span of the solid state disk.