US Patent 11335422 Semiconductor memory device and memory system

A semiconductor memory device includes: a first memory cell and switching element coupled in series between a first and second interconnect; a second memory cell and switching element coupled in series between the first and a third interconnect; a third memory cell and switching element coupled in series between the first and a fourth interconnect; and a control circuit. The control circuit is configured to: in a first operation on the first memory cell, upon receipt of a first command, apply a third voltage between the first and second voltage to the third and fourth interconnect; and upon receipt of a second command, apply the first and third voltage to the fourth and third interconnect, respectively.