US Patent 11342023 3D NAND flash and operation method thereof

An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.