US Patent 11361217 Chip and chip-based data processing method

US Patent 10073816 Native tensor processor, and partitioning of tensor contractions

US Patent 10248908 Alternative loop limits for accessing data in multi-dimensional tensors

US Patent 10430913 Approximating image processing functions using convolutional neural networks

US Patent 10504022 Neural network accelerator with parameters resident on chip

US Patent 10553207 Systems and methods for employing predication in computational models

US Patent 10698657 Hardware accelerator for compressed RNN on FPGA

US Patent 10713186 Peripheral processing device

US Patent 10725934 Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode

US Patent 10795836 Data processing performance enhancement for neural networks using a virtualized data iterator

US Patent 10810484 Hardware accelerator for compressed GRU on FPGA

US Patent 10929744 Fixed-point training method for deep neural networks based on dynamic fixed-point conversion scheme

US Patent 10936951 Machine learning through multiple layers of novel machine trained processing nodes

G06F 13/28

G06F 9/3871

G06F 9/30149

G06N 3/063

G06F 2213/0026

US Patent 10073816 Native tensor processor, and partitioning of tensor contractions

US Patent 10248908 Alternative loop limits for accessing data in multi-dimensional tensors

US Patent 10430913 Approximating image processing functions using convolutional neural networks

US Patent 10504022 Neural network accelerator with parameters resident on chip

US Patent 10553207 Systems and methods for employing predication in computational models

US Patent 10698657 Hardware accelerator for compressed RNN on FPGA

US Patent 10713186 Peripheral processing device

US Patent 10725934 Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode

US Patent 10795836 Data processing performance enhancement for neural networks using a virtualized data iterator

US Patent 10810484 Hardware accelerator for compressed GRU on FPGA

US Patent 10929744 Fixed-point training method for deep neural networks based on dynamic fixed-point conversion scheme

US Patent 10936951 Machine learning through multiple layers of novel machine trained processing nodes

G06F 13/28

G06F 9/3871

G06F 9/30149

G06N 3/063

G06F 2213/0026