Is a
Patent attributes
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Arun Babu Pallerla0
Changho Jung0
Chulmin Jung0
Jason Cheng0
Sung Son0
Venugopal Boynapalli0
Yandong Gao0
Date of Patent
June 14, 2022
0Patent Application Number
170020820
Date Filed
August 25, 2020
0Patent Primary Examiner
A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.
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