US Patent 11366951 Method for evaluating failure-in-time
Patent 11366951 was granted and assigned to Taiwan Semiconductor Manufacturing Company on June, 2022 by the United States Patent and Trademark Office.
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US Patent 11366951 Method for evaluating failure-in-time
A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.
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