US Patent 11372700 Fault-tolerant data transfer between integrated circuits

A system can include a plurality of memory devices, wherein the plurality of memory devices includes at least three memory devices. The system can include an IC. The IC can include a memory controller coupled to each of the plurality of memory devices in parallel, wherein the memory controller is configured to broadcast a read command to each of the plurality of memory devices. The IC can include an error correction circuit coupled to each of the plurality of memory devices, wherein the error correction circuit is configured to compare data bits received from the plurality of memory devices responsive to the read command and output data bits corresponding to a majority of the data bits received from the plurality of memory devices. The IC can include a consumer circuit coupled to the error correction circuit, wherein the consumer circuit receives the data bits output from the error correction circuit.