Is a
Patent attributes
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Kenneth Reneris0
Paul Accisano0
Mark G. Kupferschmidt0
Janet L. Schneider0
Date of Patent
July 5, 2022
Patent Application Number
16518668
Date Filed
July 22, 2019
Patent Citations
Patent Citations Received
Patent Primary Examiner
Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.
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