Patent attributes
A half rate bang—bang phase detector for high-speed Analog Clock and Data Recovery (CDR) is disclosed. In some embodiments, the half rate bang—bang phase detector includes a first set of flip flops. Each of the first set of flip flops is configured to receive an input data sampled at each of a four phases of a Voltage Controlled Oscillator (VCO) clock. The half rate bang—bang phase detector includes a first set of logic gates configured to generate a set of four exclusive—OR (XOR) outputs. The half rate bang—bang phase detector includes a second set of flip flops configured to generate a set of clean XOR outputs. The half rate bang—bang phase detector includes a second set of logic gates configured to generate a set of final outputs based on the set of clean XOR outputs.