Patent attributes
Methods, systems, and devices for reduced pin status register are described. An apparatus may include a first memory die and a second memory die each coupled with a data bus. The apparatus may further include a controller coupled with the first memory die and the second memory die via the data bus that is configured to transmit a first command associated with a first operation to the first memory die and a second command associated with a second operation to the second memory die. The controller may further transmit a third command concurrently to the first memory die and the second memory die, the third command requesting a first status of the first operation and a second status of the second operation. The controller may receive the first status and the second status concurrently via the data bus from the first memory die and the second memory die.