US Patent 11404538 Semiconductor memory device and method of fabricating same

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.