US Patent 11418371 Semiconductor integrated circuit, receiving apparatus, and memory device

According to one embodiment, in a semiconductor integrated circuit, the second circuit samples an amplitude of the output second signal at a plurality of timings every given cycle in a period corresponding to a second period of the pattern. The second circuit controls a parameter relating to the frequency characteristic for the first circuit according to a first magnitude relation and a second magnitude relation. The first magnitude relation is a relation between an absolute value of a first amplitude and a first threshold. The first amplitude is an amplitude sampled at a first timing among the plurality of timings. The second magnitude relation is a relation between an absolute value of a second amplitude and the first threshold. The second amplitude is an amplitude sampled at a second timing. The second timing is a timing after the first timing among the plurality of timings.