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US Patent 11418454 Computational accelerator for packet payload operations

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
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Mellanox Technologies (company)
Current Assignee
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Mellanox Technologies (company)
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11418454
Date of Patent
August 16, 2022
Patent Application Number
17204968
Date Filed
March 18, 2021
Patent Citations
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US Patent 10218645 Low-latency processing in a network node
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US Patent 10423774 System and method for establishing secure communication channels between virtual machines
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US Patent 10382350 Maintaining packet order in offload of packet processing functions
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US Patent 10715451 Efficient transport flow processing on an accelerator
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US Patent 10824469 Reordering avoidance for flows during transition between slow-path handling and fast-path handling
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US Patent 10956346 Storage system having an in-line hardware accelerator
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US Patent 10841243 NIC with programmable pipeline
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US Patent 10078613 Computing in parallel processing environments
...
Patent Citations Received
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US Patent 11606317 Table based multi-function virtualization
Patent Primary Examiner
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Natasha W Cosme
CPC Code
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H04L 29/06095
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H04L 47/2483
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H04L 49/355
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H04L 63/0272
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H04L 47/31
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H04L 63/166
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H04L 69/163
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H04L 69/22
...

Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.

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