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US Patent 11422773 Multiple busses within a systolic array processing element
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Patent
Date Filed
June 29, 2020
Date of Patent
August 23, 2022
Patent Application Number
16915937
Patent Citations
US Patent 10879904 Application specific integrated circuit accelerators
US Patent 10817260 Reducing dynamic power consumption in arrays
Patent Citations Received
US Patent 11762803 Multiple accumulate busses in a systolic array
US Patent 11842169 Systolic multiply delayed accumulate processor architecture
0
US Patent 11880682 Systolic array with efficient input reduction and extended array performance
0
US Patent 12067375 Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11422773
Patent Primary Examiner
Emily E Larocque
CPC Code
G06F 7/50
G06F 7/523
G06F 7/5443
G06N 3/063
G06N 3/04
G06N 3/08
G06F 15/8046
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