Patent attributes
An apparatus including a memory and a circuit. The memory may comprise three buffers. The circuit may be configured to allocate the three buffers in the memory based on a size of a full resolution feature map, receive a plurality of regions of interest ranked based on a feature map pyramid, generate a plurality of levels of the feature map pyramid starting from the full resolution feature map and store the levels in the buffers. The circuit may store the levels that are used by at least one of the plurality of regions of interest or do have a dependent level, the levels that are generated may be stored in the buffers in a pattern that ensures the level is stored until no longer needed to create the dependent level and enables the level to be discarded when no longer needed to create the dependent level.
