US Patent 11429534 Addressing cache slices in a last level cache
Patent 11429534 was granted and assigned to Nvidia on August, 2022 by the United States Patent and Trademark Office.
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Edits on 16 Oct, 2023
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Patent Inventor Names
James M. Van Dyke0
Kun Fang0
Prakash Bangalore Prabhakar0
Edits on 31 Aug, 2022
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US Patent 11429534 Addressing cache slices in a last level cache
Article
A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.
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Patent Jurisdiction
Patent Number
11429534
Date of Patent
August 30, 2022
Patent Application Number
17229641
Date Filed
April 13, 2021
Patent Citations
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