US Patent 11439010 Via pattern for framebuffer interfaces

This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.