US Patent 11450397 Memory system

A memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller is configured to schedule plural types of reliability countermeasure processes to be executed for the nonvolatile semiconductor memory. The plural types of reliability countermeasure processes includes at least a first reliability countermeasure process. The memory controller is configured to skip the first reliability countermeasure process to be executed when the first reliability countermeasure process is not necessary to be executed by executing an access process other than the first reliability countermeasure process to the nonvolatile semiconductor memory.