US Patent 11451234 Delay looked loop circuit and method of measuring delay

A delay locked loop (DLL) circuit that includes a delay line, a pattern injecting circuit, a pattern detecting circuit and a counter is introduced. The delay line may align a phase of a reference clock signal with a phase of a feedback clock signal. The pattern injecting circuit injects a predetermined pattern to the reference clock signal to generate an injected reference clock signal and asserts the injected reference clock signal to the delay line. The pattern detecting circuit detects the predetermined pattern in the feedback clock signal. The counter determines a delay of the delay locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. A method of measuring a delay of the DLL circuit is also introduced.