US Patent 11460876 Methods and devices for fault tolerant quantum gates

A method includes obtaining a plurality of entangled qubits, with high fault tolerance, represented by a lattice structure. The lattice structure includes a plurality of contiguous lattice cells. A first subset of the plurality of entangled qubits defines a first plane, and a second subset of the plurality of entangled qubits defines a second plane that is parallel to and offset from the first plane. The plurality of entangled qubits includes a defect qubit that is entangled with at least one face qubit on the first plane and at least one edge qubit on the second plane.