Patent attributes
A semiconductor device includes an image recognition device having a convolution arithmetic processing circuit. The convolution arithmetic processing circuit includes a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation. The integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N. The product calculation circuit can calculate data of N×N all at once.
