US Patent 11463284 Programmable correlation computation system

Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.