Patent attributes
A solid-state switch assembly includes a base plate and an electrically insulating layer affixed to the base plate. First, second, third, and fourth power traces are affixed to the electrically insulating layer. First semiconductor devices are arranged on the first power trace to control power flow between the first power trace and the second power trace, second semiconductor devices are arranged on the second power trace to control power flow between the second power trace and the third power trace, and third semiconductor devices are arranged on the third power trace to control power flow between the third and fourth power traces. A first signal conductor communicates with the first semiconductor devices. A second signal conductor communicates with the second semiconductor devices. A third signal conductor communicates with the third semiconductor devices.
