US Patent 11476868 Dual loop SAR ADC with process driven architecture

A dual-loop analog to digital converter (ADC) includes an asynchronous inner loop including first and second comparators and a state machine, where outputs of the first and second comparators are coupled to inputs of the state machine, and where outputs of the state machine are cross-coupled to enable ports of the first and second comparators. The ADC includes a synchronous outer loop including a successive approximation register (SAR), a digital to analog converter (DAC), and the first and second comparators, where the outputs of the first and second comparators are coupled to inputs of the SAR, an N-bit output of the SAR is coupled to an N-bit input of the DAC, and a differential output of the DAC is coupled to inputs of the first and second comparators, where a state of the state machine is independent of the state of the SAR.