US Patent 11482290 Controller and memory system including the controller

A controller including a test manager configured to output a program command for performing a program operation of a memory block and a suspend command for stopping the program operation, and a memory interface configured to transmit the program command to a memory device including the memory block, and transmit the suspend command to the memory device after a set time elapses. The test manager outputs a read command for reading memory cells included in the memory block, the memory interface calculates a count value by counting data output from the memory device in response to the read command, and the test manager generates status information on the memory block according to the count value.