Patent attributes
A method of designing 3D Integrated Circuits including: partitioning at least one design into at least two levels, a first and second level, where the first level includes logic, the second level includes memory; and then receiving a first placement of at least portion of the second level, where the first placement includes a placement of a first memory array, where the Circuit includes a plurality of connections between the first level and second level; performing a second placement of the first level based on the first placement, the performing a second placement includes using a placer computer executed, where the placer is a part of a Computer Aided Design tool, where the logic includes a first logic circuit configured to write data to the first memory array, and where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array.
