Patent attributes
A semiconductor structure includes an array of two-port (TP) SRAM cells, each of which includes a write port and a read port. The write port includes two write pass gate (W_PG) transistors, two write pull-down (W_PD) transistors, and two write pull-up (W_PU) transistors. The array of TP SRAM cells includes first and second TP SRAM cells whose write ports abuts each other. Two W_PG transistors of the first and second TP SRAM cells share a common gate electrode. Source/drain electrodes of two W_PD transistors of the first and second TP SRAM cells share a common contact. The first TP SRAM cell includes a Vss conductor connected to the common contact. The second TP SRAM cell includes a write word line (W_WL) landing pad connected to the common gate electrode. The Vss conductor and the W_WL landing pad are located at a first metal layer.
