US Patent 11495303 Semiconductor memory device

A semiconductor memory device includes a first conductive layer, a first and a second semiconductor layer opposed to the first conductive layer, a first and a second electric charge accumulating portion disposed between the first conductive layer and the first and the second semiconductor layer, and a first and a second bit line electrically connected to the first and the second semiconductor layer. A distance from a center position of the first conductive layer to the second semiconductor layer is smaller than a distance from the center position of the first conductive layer to the first semiconductor layer. When a read operation is executed on a first memory cell including the first electric charge accumulating portion and a second memory cell including the second electric charge accumulating portion, a voltage of the second bit line is larger than a voltage of the first bit line.