US Patent 11502102 Three-dimensional memory devices and fabrication methods thereof

Embodiments of a method for forming a three-dimensional (3D) memory device includes the following operations. First, a channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. A semiconductor channel is formed by filling the channel hole with a channel-forming structure. The plurality of first layers is removed. A plurality of conductor layers is formed from the plurality of second layers. Further, a gate-to-gate dielectric layer is formed between the adjacent conductor layers, the gate-to-gate dielectric layer including at least one sub-layer of silicon oxynitride.