Is a
Patent attributes
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
December 27, 2022
Patent Application Number
17173127
Date Filed
February 10, 2021
Patent Citations
Patent Primary Examiner
The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.
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