US Patent 11552028 Chip packaging method and chip packaging structure

A method for packaging a chip and a chip packaging structure. A passivation layer is provided on bonding pads of a wafer, a first metal bonding layer is formed on the passivation layer, and a second metal bonding layer is formed on a substrate. The substrate and the wafer are bonded via the first metal bonding layer and the second metal bonding layer, and are packaged as a whole. A first shielding layer is provided on the substrate, and the first shielding layer is in contact with the second metal bonding layer. After the wafer and the substrate are bonded, the wafer is subject to half-cutting to expose the first metal bonding layer. Then, the second shielding layer electrically connected to the first metal bonding layer is formed.