Patent attributes
A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.
