US Patent 11563454 Selective time-interleaved analog-to-digital converter for out-of-band blocker mitigation

Technologies directed to a receiver circuit with selective time-interleaved analog-to-digital converters (ADCs) are described. The receiver circuit includes a first ADC, a second ADC, and a digital processing circuit coupled to the first ADC and second ADC that operates in a first mode or a second mode. In the first mode the first ADC receives a first signal and generates first samples at a first sampling frequency. The digital processing circuit processes the first samples. In the second mode, the first ADC and the second ADC both receive a second signal and collectively generate second samples at a second sampling frequency that is greater than the first sampling frequency. The digital processing circuit processes the second samples.