US Patent 11568219 Multiple accelerators for neural network

Technologies are described for multiple accelerators for a neural network, and methods thereof. In an example implementation, a neural network can be mapped to a system comprising a control unit and multiple accelerators, where the controller unit controls each accelerator's behavior, sends data to and receives data from each accelerator through the interconnections. Sub-networks may be created by grouping several network layers or dividing a network layer into multiple sub-layers depending on data to be processed and memory capacity of each accelerator. Accelerators have internal storage, thus, do not require external memory.