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US Patent 11569158 Semiconductor package
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Patent
Date Filed
April 13, 2021
Date of Patent
January 31, 2023
Patent Application Number
17228784
Patent Citations
US Patent 10475759 Integrated circuit structure having dies with connectors of different sizes
US Patent 10510704 Package structure and method of manufacturing the same
US Patent 10510710 Bump-on-trace interconnect
US Patent 10515917 Bump on pad (BOP) bonding structure in semiconductor packaged device
US Patent 10522438 Package structure having under ball release layer and manufacturing method thereof
US Patent 10522488 Patterning polymer layer to reduce stress
US Patent 10535609 Package structure and method for forming the same
US Patent 10622336 Manufacturing method of semiconductor package
US Patent 10602621 Method of manufacturing circuit board
US Patent 11145611 Semiconductor package and method of manufacturing the same
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11569158
Patent Primary Examiner
Nicholas J Tobergte
CPC Code
H01L 23/3171
H01L 23/49822
H01L 23/49833
H01L 23/49838
H01L 23/5385
H01L 23/5386
H01L 24/16
H01L 23/49816
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