US Patent 11569823 DLL having edge combiner with matched loads

A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.