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US Patent 11575440 Computing viable paths through an optical network

Patent 11575440 was granted and assigned to Ciena (company) on February, 2023 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Patent Applicant
Ciena (company)
Ciena (company)
Current Assignee
Ciena (company)
Ciena (company)
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11575440
Date of Patent
February 7, 2023
Patent Application Number
17099927
Date Filed
November 17, 2020
Patent Citations
‌
US Patent 10237011 Methods and apparatus for pre-programming layer-0 service turn up speeds for photonic service provisioning or restoration
‌
US Patent 10411806 Gridless optical routing and spectrum assignment
‌
US Patent 10455300 Management of flexible grid and supercarriers in optical networks using a data model
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US Patent 10560212 Systems and methods for mesh restoration in networks due to intra-node faults
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US Patent 10536216 Service synchronization in retain home path scenarios in a control plane network
‌
US Patent 10038495 Systems and methods for statistical multiplexing with OTN and DWDM
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US Patent 10097306 Path computation systems and methods in control plane based networks for photonic layer topologies
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US Patent 10110438 Control plane discovery of services
...
Patent Primary Examiner
‌
Brenda H. Pham
CPC Code
‌
H04B 10/27
‌
H04B 10/03
‌
H04Q 11/0001

Path computation systems and methods are provided herein. According to one embodiment, a method includes obtaining topological information representing a topology of at least a portion of a network. The topological information includes one or more nodes and one or more links, each link configured to connect a node with a neighboring node. Each node includes a plurality of internal components and a plurality of connections configured to interconnect the internal components. The method further includes running path computation through the topological information to determine a plurality of paths from a first internal component to a second internal component. Also, the method includes applying elimination rules during the path computation to filter out one or more paths detected as being invalid. The elimination rules are based on one or more predetermined path sequences that include at least two hops involving an unviable sequence of specific types of internal components.

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