US Patent 11575494 Link status detection for a high-speed signaling interconnect

A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.