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US Patent 11580030 Devices, systems, and methods of logical-to-physical address mapping
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Patent
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Date Filed
August 18, 2020
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Date of Patent
February 14, 2023
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Patent Application Number
16996827
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Patent Citations
US Patent 10228878 Wear leveling in non-volatile storage
US Patent 10552085 Techniques for directed data migration
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US Patent 10222984 Managing multi-granularity flash translation layers in solid state drives
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Patent Citations Received
US Patent 11907569 Storage deveice that garbage collects specific areas based on a host specified context
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US Patent 12093533 Memory management of nonvolatile discrete namespaces
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US Patent 11972153 Techniques for managing writes in nonvolatile memory
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US Patent 11914523 Hierarchical storage device with host controlled subdivisions
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US Patent 11907134 Nonvolatile memory controller supporting variable configurability and forward compatibility
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11580030
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Patent Primary Examiner
Sanjiv Shah
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CPC Code
G06F 2212/2022
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G06F 12/10
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G06F 12/00
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G06F 12/1027
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G06F 3/0688
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G06F 2212/222
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G06F 3/0679
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G06F 2212/7201
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G06F 12/0246
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G06F 2212/657
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