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US Patent 11581287 Chip scale thin 3D die stacked package
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Is a
Patent
Current Assignee
Intel
Date Filed
June 29, 2018
Date of Patent
February 14, 2023
Patent Applicant
Intel
Patent Application Number
16024700
Patent Citations
US Patent 10026671 Substrate design for semiconductor packages and method of forming same
US Patent 10490528 Embedded wire bond wires
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11581287
Patent Primary Examiner
Mamadou L Diallo
CPC Code
H01L 2225/06582
H01L 2225/06541
H01L 2225/06562
H01L 2225/06517
H01L 2224/16146
H01L 2224/13147
H01L 23/49816
H01L 24/20
H01L 23/13
H01L 2924/15151
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