US Patent 11581321 SRAM structures with improved write word line placement

Integrated circuit (“IC”) layouts are disclosed for improving performance of memory arrays, such as static random access memory (“SRAM”). An exemplary IC device includes an SRAM cell and an interconnect structure electrically coupled to the SRAM cell. The interconnect structure includes a first metal layer electrically coupled to the SRAM cell that includes a bit line, a first voltage line having a first voltage, a word line landing pad, and a second voltage line having a second voltage that is different than the first voltage. The first voltage line is adjacent the bit line. The word line landing pad is adjacent the first voltage line. The second voltage line is adjacent the word line landing pad. A second metal layer is disposed over the first metal layer. The second metal layer includes a word line that is electrically coupled to the word line landing pad.