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US Patent 11593109 Sharing instruction cache lines between multiple threads
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Patent
Date Filed
June 7, 2021
Date of Patent
February 28, 2023
Patent Application Number
17341209
Patent Citations
US Patent 10901627 Tracking persistent memory usage
US Patent 10163510 System and method for atomic persistence in storage class memory
US Patent 10534616 Load-hit-load detection in an out-of-order processor
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11593109
Patent Primary Examiner
William B Partridge
CPC Code
G06F 9/32
G06F 9/44563
G06F 9/3808
G06F 9/3851
G06F 12/0806
G06F 12/084
G06F 12/0842
G06F 12/0875
G06F 2212/452
G06F 2212/655
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